MIO Routing Diagram

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

There is often high flexibility as to where to route the I/O signals for a peripheral controller. In a few cases, the IOP interfaces and signals are only available on the MIO pins (e.g., quad SPI). In other cases, I/O signals are only available on the EMIO interface (e.g., LPD DMA handshake control).

The PMC peripheral interface signals can only be routed to a PMC MIO pin, or the EMIO port signals. For LPD peripheral interface signals, the first MIO pin routing decision is to select between the PMC and the LPD MIO multiplexers. The selection is done using the LPD_MIO_Sel register.

The following figure provides a general overview of the routing architecture.

Figure 1. MIO Routing Diagram