Transaction Checking Operations

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

For every read and write transaction, the XPPU determines if the transaction is allowed to proceed with a fine grain of control of specific addresses. If the transaction is allowed, it proceeds normally. If the transaction is not allowed, it asserts an error flag that is detected downstream.

An AXI transaction request is allowed to access the address space defined by an APERPERM_xxx register (example APERPERM_000 ) if these conditions are satisfied:

  • The AXI transaction SMID fits one (or more) of the profiles defined in the SMID_xx registers
  • The AXI address selects an aperture that enables the selected SMID_xx register and its [permission] bit field
  • The transaction request satisfies the [TRUSTZONE] register bit setting