PCIe Resets on MIO Pins

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The following table includes the PCIe reset signals routed from the MIO pins to the PCIe controllers (device options). The reset pins are shown in the tables of the MIO-at-a-Glance Tables section.

Table 1. PCIe Controller Reset Input Signals
Signal Name I/O MIO-at-a-Glance Table Notes
PCIE0_RESET_b Input RST0 Reset to PCIe controller 0
PCIE1_RESET_b Input RST1 Reset to PCIe controller 1