Lock-Step Architecture

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
Release Date
1.6 English

The RPU lock-step architecture includes comparison and synchronization logic to continually compare the data coming out of the CPUs. When the Cortex-R5F processors are configured to operate in the lock-step configuration, the CPU0 interfaces with the system interconnect and the local memories (including the TCMs and caches).

When the Cortex-R5F processors are in the lock-step mode, there should be code in the reset handler to ensure that the distributor within the generic interrupt controller (GIC) dispatches interrupts only to CPU0.

Important: During the lock-step operation, all of the TCMs become available for a total of 256 KB. The configuration of the TCMs is controlled by the RPU_DUAL_CSR GLOBAL_CNTL [TCM_COMB] register bit.

The RPU processor lock-step architecture is shown in the following figure.

Figure 1. RPU Lock-Step Architecture