System Perspective

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The PMC includes system-level reset functionality. This includes hardware circuits, the EAM, and the CRP register set. The LPD, FPD, and CPM have simpler reset controllers that service the individual processors, interconnect, memories, and peripherals. These functional units are introduced in this section and are shown in the Reset Circuitry, EAM, and JTAG TAP Controller section.

PMC Hardware Reset Circuitry

The PMC hardware reset circuitry receives input from the POR_B pin and the PMC critical power supplies to generate the external POR.

PMC Error Accumulator Module

The PMC error accumulator module (EAM) receives system errors from many parts of the system. The EAM can turn these errors into an internal POR or a system reset (SRST). There are approximate 50 system error signals routed to the PMC_GLOBAL.PMC_ERR1_STATUS and PMC_ERR2_STATUS registers. A system reset only resets the mask registers. A POR resets both the mask and status registers.

Reset Controllers

The PMC reset controller drives both the device-level resets and the individual PMC block resets. The controller is shown in the Reset Circuitry, EAM, and JTAG TAP Controller section.

See the table in the Device-Level Resets section.

The LPD, FPD, and CPM reset controllers are simpler than the PMC reset controller. They are used to reset individual blocks in their respective power domain.