The following tables list the implementations of the RPU processor engine components.
| Device Generation | CPU Core | CPU Core Extensions | Breakpoints | Watchpoints | Tightly Coupled Memory per CPU Core |
|---|---|---|---|---|---|
| UltraScale+ MPSoC | Two CPU cores with lockstep option. Arm Cortex-R5F v-7R instruction set Version AT570-r1p3-00rel0 |
Single and double precision FPU with VFPv3 instructions. | – | – | iCache: 32 KB (4 way) dCache: 32 KB (4 way) TCM_A: 64 KB w/ECC TCM_B0: 32 KB w/ECC TCM_B1: 32 KB w/ECC |
| Versal device | Two, dual-cluster cores with lockstep option. Arm Cortex-R5F Arm v-7R instruction set Version AT570-r1p3-00rel0 |
Single and double precision FPU with VFPv3 instructions. | Eight pair per core. | Eight pair per core. | iCache: 32 KB (4 way) dCache: 32 KB (4 way) TCM_A: 64 KB w/ECC TCM_B0: 32 KB w/ECC TCM_B1: 32 KB w/ECC |
| Device Generation | RPU Generic Interrupt Controller | MPU | CPU System Interface | LLPP Interface |
|---|---|---|---|---|
| UltraScale+ MPSoC | Each CPU has 64b AXI port to LPD switch. | Programmable MPU per core with 16 regions each. | 64-bit AXI to OCM switch interface for each core. | Connected to GIC. |
| Versal device |
PL-390 |
Programmable MPU per core with 16 regions each. | Two 64-bit AXI to OCM switch interfaces. | Connected to GIC. |