Block Diagram

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

All clock frequency dividers have the same functionality and programming model. The basic design is shown in the following figure.

Note: Not all of the PLL source clock choices shown are always available. See the register reference. For example, the RPLL and APLL reference clocks cannot drive the PMC clock frequency dividers.
Figure 1. Clock Frequency Divider Block Diagram