PLL Clock Generator Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The PLL clock generator registers are included in four sets of registers: PMC, LPD, FPD, and CPM. The following table lists the controller names and register sets. The PLL clock is from the REF_CLK input pin.

Table 1. PLL Clock Generator Control Registers
PLL Clock Output Name Power Domain Registers
Control Register Configuration Register PLL Status Fields
Fields: [RESET], [BYPASS], [FBDIV], [CLKOUTDIV], [PRE_SRC], [POST_SRC] Fields: [RES], [CP], [LFHF], [LOCK_CNT], [LOCK_DLY] Fields: [xPLL_LOCK], [xPLL_STABLE]
PPLL_CLK PMC PMCPLL_CTRL PMCPLL_CFG PLL_STATUS
NPLL_CLK NOCPLL_CTRL NOCPLL_CFG
RPLL_CLK LPD RPLL_CTRL RPLL_CFG PLL_STATUS
APLL_CLK FPD APLL_CTRL APLL_CFG APLL_STATUS
CPLL_CLK PL CPLL_CTRL CPLL_CFG CPLL_STATUS