MIO Routing Control Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

There are several routing control mechanisms for software.

  • MIO multiplexer control registers in PMC and LPD
  • LPD peripheral I/O can route to the LPD or to the PMC MIOs
  • Miscellaneous MIO multiplexing control registers
  • PMC SYSMON ADC channel input for voltage measurements

MIO Multiplexer Control Registers

The each multiplexer pin includes a routing control register:

LPD Peripheral I/O Routing to PMC

The LPD peripheral I/O signal can often be routed to either the PMC or LPD MIO multiplexers using the LPD_IOP_SLCR LPD_MIO_Sel register. Routing options are included for the I/O signals for SWDTs, I2C, CANFD, UART, TTC, SPI, and GEM MDIO.

Miscellaneous MIO Multiplexing Controls

There are several special-case I/O signal routing controls.

  • SWDT reference clock select (MIO, EMIO, or APB interface); see System-Level Registers
  • TTC reference clock source select; see TTC_Clk_Sel
  • PSM wake-up input on MIO[0:5]

Loopback Functionality

The LPD MIO multiplexer includes the MIO_Bank2_Loopback register for some I/O peripherals.

  • SPI controllers
  • UART controllers
  • CAN FD controllers
  • I2C controllers

PMC SYSMON ADC Channel Input

The PMC system monitor has analog inputs that can be connected to the PMC or LPD MIO pins.

The system monitor functionality is described in the Versal Adaptive SoC System Monitor Architecture Manual (AM006).

The system monitor registers are included in the PMC_SYSMON_CSR register module.