The LPD DMA registers are listed in the following table. The register base address for each channel is:
- Channel 0,
0xFFA8_0000
- Channel 1,
0xFFA9_0000
- Channel 2,
0xFFAA_0000
- Channel 3,
0xFFAB_0000
- Channel 4,
0xFFAC_0000
- Channel 5,
0xFFAD_0000
- Channel 6,
0xFFAE_0000
- Channel 7,
0xFFAF_0000
Register Name | Offset Address | Access Type | Description |
---|---|---|---|
ERR_CTRL |
0x000
|
RW | APB address decode error |
|
|
WTC, |
Interrupt status, mask, enable, and disable |
|
|
RW | Controls |
CH_FCI |
0x118
|
RW | Flow control interface |
CH_STATUS |
0x11C
|
R | State of channel |
CH_DATA_ATTR |
|
RW |
Data and descriptor AXI parameters |
|
|
RW |
Source descriptor words |
|
|
RW |
Destination descriptor words |
|
|
RW |
Write only data words |
|
|
RW |
Source descriptor start address |
|
|
RW |
Destination descriptor start address |
CH_RATE_CTRL |
0x18C
|
RW | Rate control count |
|
RW |
Source and destination interrupt account count |