There are many clock frequency dividers in the PMC, LPD, FPD, and CPM that provide a reference clock for each block or group of blocks. See the Clock Distribution section for an overview.
The PMC, processing system, and CPM clock dividers all have similar programming models. The clock control registers select the PLL source clock, the 10-bit frequency divider value, and enable the divider clock output. The clock divider register sets include: