The Interrupt Status register (ISR) bits are sticky and masked by the Interrupt Mask register, IMR. Non-masked interrupts are OR'd together to generate a system interrupt.
Transfer Complete
The [COMP] interrupt bit functionality depends on the interface mode and the interface activity.
This bit is always set when all the supplied data is successfully written to the requester and the transfer is about to be terminated with a stop sequence. If the [HOLD] bit is set, the [COMP] bit is also set as soon as the data is successfully written, but the transfer is not terminated at this point. This allows for combined transfers to be performed even when FIFO is implemented. If the host clears the [HOLD] bit instead of continuing the transfer, the [COMP] bit is set again during the stop sequence generation.
In manager read, this bit is set when all the requested data has been successfully read from another and the transfer is to be terminated with a stop sequence.
If FIFO is implemented and the hold bit is set, the [COMP] bit is also set as soon as all data is successfully received, but the transfer is not terminated at this point. This allows for combined transfers to be performed even when FIFO is implemented. If the host clears the [HOLD] bit instead of continuing the transfer, [COMP] bit is set again during the stop sequence generation.
In response mode, the [COMP] bit is set whenever the manager terminates the transfer by generating a stop sequence. In transmit, this bit is set whenever all the data supplied by the host is transmitted and the last byte is not acknowledged by the manager, which terminates the transfer with a stop sequence.
More Data
The DATA interrupt bit functionality depends on the direction of the data flow.
This bit is set whenever there are only two bytes left in the FIFO.
In transmitter mode, this bit is also set if the FIFO is emptied but the manager returned ACK on the last byte transmitted by the subordinate.
This bit is set whenever there are only two free locations in the FIFO.
Transfer not Acknowledged
The function of the NACK interrupt bit is dependent on the interface mode.
This bit is set whenever the accessed host responds with a NACK during address or data byte transfer.
This bit is set if the controller is in transmitter mode when a manager terminates the transfer before all data supplied by the host is transmitted.
Timeout
The TO interrupt bit is set whenever the SCL clock signal is kept low for longer time than the value that is specified by the Timeout register.
Monitor Ready
These conditions are needed to set the SLV_RDY interrupt bit:
- Interface is in manager mode
- The Control [CSLVMON] bit is set = 1
- The addressed subordinate returns an ACK
FIFO Receive Overflow
The [RX_OVF] interrupt bit applies to manager read or subordinate receiver. This bit is set whenever the FIFO is full and a new byte is received. The new byte is not acknowledged and contents of the FIFO remains unchanged.
FIFO Transmit Overflow
The [TX_OVF] interrupt bit is set when software attempts to write to the Data register more times than the FIFO depth.
FIFO Receive Underflow
The [RX_UNF] interrupt bit is set when software attempts to read from the Data register more times than the value of the Transfer Size register plus one.
Arbitration Lost
The [ARB_LOST] interrupt bit is set if the manager loses bus ownership during a transfer due to ongoing arbitration.