Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The QSPI registers are reset by a POR or by the PMC reset controller using the RST_QSPI register.

A controller reset is required when:

  • The QSPI_REF_CLK clock frequency is changed. The clock control is described in System Perspective.
  • When both the baud-rate divisor and the I/O device mode is changed. For example, a reset is required before changing from a single, or stacked device mode with a baud rate setting of 4 and then switching to the dual-parallel mode with a baud rate of 2.