Host Capabilities, Offset, and Operations Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID

AM011

Release Date

2023-10-05

Revision

1.6 English

The USB host capabilities, offset, and operations registers are located in the USB_XHCI register set at base address 0xFE20_0000. They are summarized in the following table.

CONFIG register
This register is in the AUX power well. It is only reset by the platform during a cold reset or in response to a host controller reset (HCRST).

Table 1. USB Host Capabilities, Offsets, and Operations Registers
Offset Address	Access Type	Description
`0x0000`	R	Length capability
`0x0004 0x0008 0x000C`	R	Host controller structural parameters
`0x0010 0x001C`	R	Host controller capability parameters
`0x0014`	R	Doorbell offset
`0x0018`	R	Runtime offset
`0x0020`	RW	USB command
`0x0024`	R, W1C	USB status
`0x0028`	R	Page size
`0x0034`	RW	Device notification
`0x0038 0x003C`	RW, R
`0x0050 0x0054`	RW	Device context BAAP
`0x0058`	RW	Configure