The following table shows the subsystem resets.
| Description | Reset Name | Power Domain | Register Bit Control |
|---|---|---|---|
| CRP RST_DBG register | |||
| All CoreSight components inside of the PMC and PS | [RESET] | ||
| Debug port controller | DPC_RESET | PMC | [DPC] |
| CRL RST_CPU_R5 register | |||
| RPU MPCore, and debug logic | RPU_POR_RESET | LPD | [RESET_POR_RPU] |
| TCMs, GIC, and 2x1 switch | RPU_AMBA_RESET | LPD | [RESET_AMBA] |
| RPU CPUs |
RPU_CPU0_RESET |
LPD |
[RESET_RPU1] |