There are many clocks in the device for clocking logic and I/O. This chapter describes the clocks in the PMC and processing system. This includes clock generators, clock dividers for reference clocks, and the various destinations within the device.
PMC and PS Clocks
The clocks associated with the PMC, processing system, and CPM are described in the following sections:
- The Clock Distribution shows the major internal clocks for the PMC, LPD, and FPD
- Three root clocks originate in the PMC and are described in Device Source Clocks section:
- REF_CLK (reference clock input device pin)
- PMC_IRO_CLK (PMC internal ring oscillator)
- RTC (real-time clock)
- There are five programmable PLL Clock Generators: two in the PMC and one in the LPD, FPD, and CPM
- Dozens of programmable Reference Clock Frequency Dividers are used to generate clocks for various blocks in the system
CPM Clocks
The clocks for the CPM are described in the Versal Adaptive SoC CPM CCIX Architecture Manual (AM016).
NoC, AI Engine, and DDR Memory Controller Clocks
The PMC includes four programmable clock dividers with outputs routed to the PL for general purpose use. The PMC also includes programmable clock divider outputs for the NoC, AI Engine, and DDR memory controllers.
PL Clocks
The PL includes its own clock trees that are programmed when blocks are instantiated. The PL also includes programmable clock modules that can be driven by clocks from input pins, PMC clock sources, and other sources.
The PMC clock controller includes four sets of reference clock dividers whose output is routed to the PL. The phase relationships between the clock divider outputs to the PL are not guaranteed. As a result, these PL clocks are considered as asynchronous with respect to each other in the PL, and standard clock domain crossing analysis and design techniques should be applied.
I/O and Transceiver Clocks
There are local PLLs in the XPIO and X5IO banks (for the PL, XPHY, X5IO PHY, and DDR memory controllers) and in the gigabit transceivers (GT) banks. These high-speed I/Os use PLL clocks for precision I/O timing. These I/O buffers and transceivers are introduced in the Device I/O Connectivity chapter of the Hardware Architecture section. The I/O transceiver clocks are described in their associated documents:
Clock Register Modules
The individual clock controls are managed by the PLM firmware. The PLM writes to the clock and reset register modules.