The timestamp unit (TSU) clock signal can be sourced from the LPD clock controller, an MIO pin, or a EMIO port interface signal. The TSU clock is programmed using the registers listed in System-Level Registers. There is one TSU clock, and it is shared by all the GEM controllers.
Note: The timer sync strobe registers (tsu_strobe_msb_sec,
tsu_strobe_sec, and tsu_strobe_nsec) are loaded with the value of the timer when the
input signal gem_tsu_inc_ctrl[1:0] = 2'b00. However, the timer sync strobe registers
are updated only when gem_tsu_inc_ctrl signal toggles between 2b'11 and
2'b00.
| Signal Name | Description | MIO | EMIO | |||
|---|---|---|---|---|---|---|
| MIO-at-a-Glance Table | I/O | Signal Name | I/O | Clock | ||
| GEM_TSU_CLK | TSU clock from MIO | CLK | I | – | – | – |
| GEM_PS_TSU_PL_CLK | TSU clock | – | – | I | – | |
| GEM_TSU_LB_CLK | TSU loopback clock from PL | – | – | I | – | |
| GEM_TSU_TIMER_CMP | Timer compare value | – | – | gem_tsu_timer_cmp_val | O | TSU Clk |
| GEM_TSU_INCR_CTRL0 | Increment control | – | – | gem_tsu_inc_ctrl0 | I | TSU Clk |
| GEM_TSU_INCR_CTRL1 | – | – | gem_tsu_inc_ctrl1 | TSU Clk | ||
| GEM_TSU_TIMER_CNT[93:0] | Timestamp unit timer count value | – | – | gem_tsu_timer_cnt[93:0] | O | TSU Clk |
Clock Incrementing Input
The INCR_CTRL[1:0] signals control the incrementing policy of the timer. The timer increments:
- 00: based on the gem_tsu_ms register bit value:
- gem_tsu_ms = 0: timer register increments as normal but the timer value is copied to the sync strobe register
- gem_tsu_ms = 1: nanoseconds timer register is cleared and the seconds timer register is incremented with each clock cycle
- 01: by an additional nanosecond
- 10: by one nanosecond fewer
- 11: normally