MIO-at-a-Glance Tables

MIO Device Pins

There are 78 sets of signals to control the MIO pins.

• 52 signals in the PMC MIO (banks 500 and 501)
• 26 signals in the LPD MIO (bank 502)

Signal Route Control

Many of the IOP controller and other signals are routed to the EMIO by default if they are not specifically routed to MIO pins. The routing for each MIO pin is controlled by a single register, MIO_PIN_xx. The signal routing control is managed by the PMC_IOP_SLCR and LPD_IOP_SLCR register modules.

• Register module with 52 control registers for 52 PMC MIO pins: PMC_IOP_SLCR
• Register module with 26 control registers for 26 LPD MIO pins: LPD_IOP_SLCR

PL EMIO Signal Route

Some interfaces and signals also go to the PL, and for most interfaces, these are listed in the MIO-EMIO Interface Routing Options section.

MIO Pin Assignments By Banks

The MIO pin assignments are shown in the following tables with links to the chapter sections that list the I/O interface signals.

• Bank 500 includes QSPI, OSPI, and eMMC1 boot interfaces
• Bank 501 includes SD0 and SD1 boot interfaces

• 8-bit interface is on the PMC MIO bank 500
• 16-bit and 32-bit interfaces require both PMC banks 500 and bank 501

Boot Pin Table Shading

MIO pins can be programmed for a specific boot mode. When a pin is included in a boot mode, it is shaded in the following tables. Some boot interfaces have multiple modes, which is differentiated by having two levels of cell shading. See the Boot Modes and Interfaces section for details.