GIC-500 Interrupt Controller

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The APU processor includes a local interrupt controller for managing APU processor related interrupts. It is attached to a programmable, generic interrupt controller (GIC-500) to capture system interrupts.

To manage system interrupts, the APU includes the GIC interrupt controller, which is based on the Arm GIC-500 generic interrupt controller and is compatible with the Arm GIC v3 architecture.

Local Address Space at 0xF900_0000

The APU Arm generic interrupt controller, GIC-500, includes nine register modules; for example, the shared APU_GIC_DIST_MAIN register module and the individual APU_GIC_REDIST_SGISPI register modules. All of the GIC register modules are listed in the GIC Registers section.

The GIC register modules are located in a 786 KB local address space starting at 0xF900_0000. This range is only accessible to the APU except for the APU_GIC_ITS_TRANS register module, which contains only one register that is only accessible to the CPM/PCIe to trigger a message-based interrupt (MSI).