Windowed Q&A Mode

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The Q&A token window mode requires the system software to write three one-byte responses during the first window (closed window) and a fourth byte write in the second window (open window). The value of the token responses are based on the seed, feedback, and an answer count value. The seed and feedback values are programmed by software.

The watchdog timer generates seed and feedback tokens and places them in the enable_and_status [TVAL] bit field that is read by software to calculate the four one-byte responses that are written as four different APB write transactions into the TRR register.

A good event occurs if the three correct response bytes are written in the first window in correct order followed by writing the last response byte in the second window. When the response bytes are not written in the correct order, in the correct window period, or with the correct value, it is considered a bad event.

The token answer to each question is four byte data that needs to be written byte after byte (MSB to LSB) into the TRR register. The first three writes must occur in the first window time and the last write must occur in the second window.

Note: In Q&A mode, the fail counter is always enabled and the timer can be disabled only if the fail counter value is 0.

The Q&A feature provides this challenge-response feature. The timer has a set of 32-bit registers that contain the expected response. The responses are computed at boot time and programmed into the timer. Each time the timer is cleared a new question index is loaded into the "challenge" register. The software computes the response and places it in the response register and then clears the watchdog. The timer checks the response against the register value referenced by the question index. If a value does not match, the timer reset system error signal is asserted in the PSM error aggregate module (EAM).