The controller is reset from several sources:
- Local controller reset: CANFD.SRR [SRST] bit
- Resets from the LPD reset controller
- POR and system reset comes from PMC register controls for the LPD, PS, and device pins
Each reset source has the same effect on the controller as summarized in the following table.
| Reset Name | Reset Type | APB Interface and Registers | Protocol Engine | Buffers and Acceptance Filters |
|---|---|---|---|---|
| SW_Reset [SRST] | Software | Yes | Yes | No |
|
RST_CAN0 [RESET] |
||||
| POR or PS | Hard |
Note: Because the buffers and
acceptance filters are not reset, the software needs to ensure that they are programmed
appropriately before operation.
Local CAN FD Reset Control
Write a 1 to the SW_Reset [SRST] bit (this bit is self-clearing).
CRL Reset Control
The CRL reset is not self-clearing. Write a 1 and then write a 0 to the RST_CAN0 [RESET] bit. These can be individual back-to-back writes to the programming interface.