Debug Packet Controller

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
Release Date
1.6 English

Debug Packet Controller

The debug packet controller (DPC) receives commands packets from one or more of debug host interfaces. The DPC then generates reply packets and transmits them back to the debug host. A link layer provides the communications between the debug host and the DPC. The DPC includes several features to process the command packets from the debug host.

  • Command buffers to buffer the queued command packets
  • Processing engine to process the queued instruction packets
  • FIFO captures the input stream from AXI
  • De-multiplexer and decode identifies the packet boundaries and decodes non-queued and queued packets
  • Reply buffers generate reply packets that are waiting to be transmitted out to the AXI
  • Interconnect switch to provide access to the PMC interconnect, SBI, TPIU, and CoreSight debug

Packet Processing

The command packets processed by the DPC are referred to as debug and trace packets (DTP). Each packet consists of a header, payload, and package integrity (CRC) fields. The DPC decodes the payloads to determine the commands, destinations, and any required higher level flow control and management tasks. The DPC generates response packets including data and any detected errors.

High-Speed Debug Port

The high-speed debug port (HSDP) provides a pathway to the GTY and GTYP transceivers for the Aurora. The debug port provides debugging and trace capability for the programmable logic, processing system, and AI Engines. The HSDP leverages the high-speed gigabit transceivers to make debug less intrusive to the system configuration. The solution can also support at-speed debug of PL designs through the PL ChipScopeā„¢ functionality.