The SRC DMA module reads data from the memory-mapped sources (AXI4) and writes it to the stream switch. General AXI4 transaction characteristics include:
- ARSIZE is always =
100b, indicating 128-bit data width. - The default ARLEN =
1111b, indicating 16 beats of data. The first and last command can have any ARLEN value ≤16 beats. - ARPROT[1] is always = 0, indicating a secure command.
- ARCACHE[1] is always = 1, indicating upsizing is allowed.
- ARID is not used by the SRC DMA module because the thread is single.
- ARBURST defaults to
01b, indicating an INCR burst. There is a register option to change the burst type to FIXED (ARBURST =00b).
The DMA read transfer begins when the PMC_DMA_SRC_SIZE register is written with a non-zero value.
The address must align to 16 byes and the size must be a multiple of 16 bytes.