SSI Multiple Super Logic Regions

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The programmable logic within a die is defined as a super logic region (SLR). Multiple SLR silicon die can be combined into one package to provide a very large amount of programmable logic. The SSI device provides a primary SoC environment connected to multiple silicon die with their SLRs of PL using an interposer. The base die provides SoC functionality with its own PL primary SLR. Each secondary die includes secondary SLR for more PL configurable hardware.

The features and hardware architectures of the multi-SLR devices are listed in this section. The software design is described in the Versal Adaptive SoC System Software Developers Guide (UG1304).

Primary Silicon Die Features

The primary die includes the SoC functionality that controls the entire device.

  • RPU and APU processing system
  • Platform management controller (PMC)
    • JTAG and PL configuration hardware
    • Boot interfaces (flash, JTAG, and SMAP)
    • RCU BootROM code, PMC running PLM firmware
    • PMC RAM
    • I/O peripheral controllers
  • NoC interconnect
  • DDR memory controllers
  • Programmable logic
  • Integrated hardware (device options)

Secondary Silicon Die Features

The secondary die are dominated by the PL, but include:

  • Simplified platform management controller (PMC) with:
    • JTAG and PL configuration hardware
    • RCU BootROM code, PMC running PLM firmware
    • PMC RAM, security units
  • NoC interconnect
  • PL SLR

Board Development Considerations

There are several development considerations for multi-SLR devices.

  • Dedicated pins
  • The system power domain (SPD) is required to boot SLR devices.

Additional board information for multi-SLR devices is included in the Versal Adaptive SoC PCB Design User Guide (UG863).

Dedicated Pins

In SSI technology devices, there multiple dedicated pins for the additional SLR silicon.

In some multi-SLR SSI devices a second REF_CLK input pin must be driven. In some cases, multiple mode pins and other dedicated pins, such as the POR_B and PUDC_B, must be driven for the secondary SLRs.

JTAG TAP Instruction Register Lengths

For SSI technology multi-SLR devices, the JTAG TAP instruction register length varies. The boundary-scan operations data register definitions and instruction register length are given in the BSDL files.

Table 1. JTAG TAP Instruction Lengths
Device Instruction Register Length
1 SLR 6 bits
2 SLRs 14 bits
3 SLRs 21 bits
4 SLRs 28 bits