PL-PMC GPI and GPO Port Signals

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The PMC includes 32 general-purpose input signals from the PL and 32 general-purpose output signals to the PL. The input signals can be unmasked to generate an interrupt to the PPU processor running the PLM firmware. The state of the input signals can be read using the interrupt status register with or without the need to enable interrupts.

GPI Signals

The 32 GPI signals are routed from the PL to the interrupt status register. An active input signal is latched into the sticky PL_PMC_GPI_ISR status register. Additional registers to mask this input include registers in the PMC_GLOBAL register module at base address 0xF111_0000:

  • Mask register: PL_PMC_GPI_IMR at offset 0x0914, read-only
  • Enable register: PL_PMC_GPI_IER at offset 0x0918, read-only
  • Disable register: PL_PMC_GPI_IDR at offset 0x091C, read-only
  • Trigger register: PL_PMC_GPI_ITR at offset 0x0920, read-only

GPO Signals

The 32 GPO signals routed from the PMC to the PL is driven High and Low by PLM firmware using the PMC_GLOBAL PMC_PL_GPO register.