GTY and GTYP Pipe Transceivers

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

Sixteen high-speed pipe transceivers are grouped into four quad banks. The transceiver pins can connect to several interfaces.

  • PCIe┬« controller 0 in the CPM
  • PCIe controller 1 in the CPM
  • High-speed debug port (HSDP), single channel
  • PL interface (this path is available only for GTY XPipe transceivers used with CPM4)

Connections to the transceivers are illustrated in the DPC Interfaces section of the Debug Packet Controller chapter.

CPM Documentation

The details of the CPM implementation are available in these documents:

  • Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)
  • Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347) (includes pipe transceiver signal assignments)