System-level Control Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID: AM011
Release Date: 2023-10-05
Revision: 1.6 English

There are several registers to control I/O routing, and the APB programming interface.

Table 1. CAN FD SLCR Registers
Description	Register	Bit Fields	Offset Address	Access Type
Reference clock controls	CRL CAN0_REF_CTRL CRL CAN1_REF_CTRL	[SRCSEL], [DIVISOR], and [CLKACT]	`0x0138` `0x013C`	RW
Software reset control	CRL RST_CAN0 CRL RST_CAN1	[RESET]	`0x0328` `0x032C`	RW
PMC MIO pin multiplexing routing	PMC_IOP_SLCR MIO_PIN_0 (0 to 51) (see Input Buffer Control Registers section)	[L0_SEL], [L1_SEL], [L2_SEL], and [L3_SEL]	`0x0000`+	RW
LPD MIO pin multiplexing routing	LPD_IOP_SLCR MIO_PIN_0 (see Input Buffer Control Registers section)	[L0_SEL], [L1_SEL], [L2_SEL], and [L3_SEL]	`0x0000`+	RW
MIO bank select: 0: PMC pin bank 1: LPD pin bank	LPD_IOP_SLCR LPD_MIO_Sel	[CAN0_SEL], and [CAN1_SEL]	`0x0410`	RW
MIO loopback enable: 0: No loopback 1: CAN0 ↔ CAN1	LPD_IOP_SLCR MIO_Bank2_Loopback	[CAN0_LOOP_CAN1]	`0x200`	RW
Programming interface parity error: 0: no error 1: parity error	LPD_IOP_SLCR PARITY_ISR	[perr_can0_apb], and [perr_can1_apb]	`0x0714`	RW