Command, DMA, and Data Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID

AM011

Release Date

2023-10-05

Revision

1.6 English

The following table lists the SD_eMMC controller registers for the system DMA unit and command controls.

Note: These registers are defined with multiple data widths. However, all registers are accessed as 32-bit read/write transfers with addresses aligned on a 32-bit boundary.

Table 1. SD_eMMC Command, DMA, and Data Registers
Register Name	Width	Offset Address	Type	Description
Register-based DMA
SDMA_ADDR_L SDMA_ADDR_H	16 16	`0x000` `0x002`	RW	Dual-use, bits [15:0] for system DMA address or auto CMD23 argument 2 Dual-use, bits [31:16] for system DMA address or auto CMD23 argument 2
BLK_SIZE	16	`0x004`	RW	Configure the number of bytes in a data block
BLOCK_COUNT	16	`0x006`	RW	Data block size and DMA/CRC enable
DATA_PORT	32	`0x020`	RW	Read/write the block buffer
Command Registers
ARGUMENT1_L ARGUMENT1_U	16 16	`0x008` `0x00A`	RW	Lower bits [15:0] of CMD argument Higher bits of SD command argument
TRANSFER_MODE	16	`0x00C`	RW	Control the operations of data transfers
CMD	16	`0x00E`	RW	Controller commands
AUTO_CMD12_ERR_STS	16	`0x03C`	R	Indicate CMD12 response error of auto CMD12 and CMD23 response error of auto CMD 23
Responses
RESP0_L RESP0_U (0 to 3 response pairs)	16 16	`0x010`+ `0x012`+	R	SD command responses 0, 1, 2, and 3
Force Event
FE_AUTO_CMD12_EIS FE_ERR_INTR_STS	16 16	`0x050` `0x052`	W R, W	Port to write to the auto CMD Error Status register Port to write to the Error Status register
Descriptor DMA
ADMA_ERR_STS	8	`0x054`	R	When the ADMA error interrupt occurs, this register holds the ADMA state in the ADMA error states field and the ADMA system address holds the address around the error descriptor
ADMA_ADDR_0 ADMA_ADDR_1 ADMA_ADDR_2 ADMA_ADDR_48	16	`0x058` `0x05A` `0x05C` `0x05E`	RW	ADMA system address [15:2], word aligned ADMA system address [31:16] ADMA system address [47:32] ADMA system address [48], transaction context