The SRC DMA interrupts in the DMA_SRC_ISR register are summarized in the following table. These interrupts are not used during normal operation, but can provide information for test and debug.
| Interrupt | Bit | Description |
|---|---|---|
| [MEM_DONE] | 0 | The DMA has completed current command of all reads of the flash memory |
| [DONE] | 1 | DMA has completed a command |
| [AXI_RDERR] | 2 | Error reading data from flash controller |
| [TIMEOUT_STRM] | 3 | Timeout counter 1 expired; flash controller is stalled |
| [TIMEOUT_MEM] | 4 | Timeout counter 2 expired; DMA is stalled |
| [THRESH_HIT] | 5 | FIFO watermark hit |
| [INVALID_APB] | 6 | APB programming interface address decode error |