The CCI core registers are summarized in the following table.
| Register Name | Access Type | Description |
|---|---|---|
| ctrl_ovr | RW | Fail-safe overrides |
| secr_acc | RW | Non-secure transaction access enables |
| status | R | Snoop enables timings |
| impr_err | RW | Imprecise signaled errors |
| qos_threshold | RW | Read and write QoS thresholds for high-priority requests |
| pmu_ctrl | RW, R | Performance monitoring unit controls |
| Egress Port Control for Six Ports | ||
|
|
RW, R | Snoop and DVM request issue control |
|
|
RW | Override shareable characteristics of normal transaction |
|
|
RW | Override value for reads |
|
|
RW | Override value for writes |
|
|
RW | Permitted outstanding transactions (OT) |
| Event Control for Eight Event Modules | ||
|
|
RW | Event codes for events and interface |
|
|
RW | Event counter value |
|
|
RW | Event counter enable |
|
|
RW | Event overflow flag |