Network On Chip

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The TRM introduces the network on chip (NoC) interconnect and includes it in high-level subsystem block diagrams, but does not explain its implementation or behavior.

See the NoC product guide for its descriptions, guidance on configuration, and performance tuning, Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313). The registers are included in the Versal Adaptive SoC NoC and Integrated Memory Controller NPI Register Reference (AM019).


The NoC is configured using the AMD Vivado™ IP integrator. Configuration data is written to the NoC units via the NPI programming interface.