Programming Considerations

Versal Adaptive SoC Technical Reference Manual (AM011)

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A DMA transfer is initiated by writing to the SRC_SIZE or DST_SIZE register.

The SRC DMA module includes a [last_word] field in the SRC_SIZE register along with the [size] field. This allows software to tag the command as the last command. Consequently, the secure stream switch DATA_INP_LAST hardware signal is asserted when the last data word is presented to the streaming interface.

Data transfer requests that bridge across the AXI4 4 KB address boundary are divided into multiple transfers by the DMA module hardware to avoid sending AXI4 transfer requests that cross the 4 KB address boundary. The DMA module issues multiple transaction requests for one command. The length of the data transfer request is defined in the DST/SRC_SIZE [size] register field.

Note: The DST_SIZE and SRC_SIZE [size] fields are used to specify the number of 32-bit words that the DMA module transfers. The transfer size must be a multiple of 16 bytes (4 words). The memory address must also be aligned to 16 bytes.

The DST/SRC_SIZE [size] register field can also be read to determine dynamic progress of the active transfer command.

For the SRC DMA module, the SRC_SIZE [Size] field indicates how many bytes still need to be fetched from the AXI4 address space. This relates to the AXI4 side only. Any data associated with a previous AXI4 transaction could still be resident in the SRC data FIFO. When the SRC_SIZE [size] field reaches 0, this means that all outstanding AXI4 reads have completed that are associated with the current DMA command.

For the DST DMA module, when the DST_SIZE [size] field goes to 0, this implies the entire DMA transfer has completed.

Note: It is not possible to have more than two outstanding commands into a command FIFO. If the software tries to write a command into a full FIFO, the write is ignored and an interrupt is generated.

The SRC_CTRL1 [FIFO_thresh] register field has a reset value of 80h, which indicates 128 entries. This setting prevents the SRC_ISR [FIFO_THRESH_HIT_INT interrupt bit being set at start-up. Software can set this to 0 to trigger an interrupt on the FIFO going empty if required.

If DMA_SIZE is written with a 0 value, the DMA is done immediately and sets the DMA_DONE_INT as well as the DMA_MEM_DONE_INT bit.

The 4 KB PMC_DMA register module is equally divided into two separate address spaces. SRC DMA registers start at offset 0x000 and DST DMA registers start at offset 0x800. If software accesses an unimplemented register, the corresponding SRC or DST AXI bus response error interrupt status bit will be set.

If a loopback mode is being used with SRC data being looped around in the SS and presented to the DST channel, the software should always start the DST channel before starting the SRC channel. This ensures that the DST channel is always ready once the first piece of data is presented at its SS interface. The SIZE of the SRC and DST transfers must be identical.

For applications where large numbers of outstanding AXI commands might lead to system congestion, this number can be limited via the APB register MAX_OUTS_CMD.