PMC Functional Units

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The following table lists the PMC functional units.

Table 1. PMC Functional Units
Unit Description Link
PMC Compute Resources
ROM code unit (RCU) Executes BootROM code after a POR or system reset ROM Code Unit
Platform processing unit (PPU) Executes platform loader and manager (PLM) firmware Platform Processing Unit
PPU RAM 384 KB memory for use by PLM Integrated Processor Memory
PMC RAM 128 KB system memory for use by PLM PMC RAM
PMC DMA 0 and 1 Streams data between secure switch and main switch PMC DMA Units and Stream Switch
Support Units    
IPI Inter-processor interrupts Inter-Processor Interrupts
System interrupts System interrupts to PPU and PSM interrupt controllers System Interrupts
Service request registers Runtime service requests Software Platform Service Requests
System EAMs PMC and PSM error accumulator modules (EAM) System Errors
Interconnect (INT) Switches: main, I/O peripheral, auxiliary, and APB Interconnect
PMC_XMPU Memory protection unit (XMPU) for PMC_RAM and SBI Xilinx Memory Protection Unit


Peripheral protection unit for PMC and NPI-based register modules Xilinx Peripheral Protection Unit
APB Register programming interface: 32-bit single read/write APB, AXI Programming Interfaces
NPI Register programming interface: 32-bit with read/write burst NPI Programming Interface
PL CFU PL configuration frame unit PL Configuration, CFU Programming Interface
eFUSE controller

Controller for eFUSE array

eFUSE cache

Cache of the eFUSEs

PMC_SBI Boot interface works with SelectMAP and JTAG data flows

SBI for JTAG and SelectMAP.

Supervised Boot Interfaces
JTAG TAP interface

Serial TAG test access port controller for boundary scan and AMD opcodes

JTAG TAP Controller
SelectMAP 8, 16, or 32 bit interface SelectMAP Boot Mode
SBI Facilitates booting via SelectMAP and JTAG SBI for JTAG and SelectMAP
Flash Memory Boot Interfaces
OSPI Octal SPI 8-bit interface OSPI Flash Boot Mode
QSPI Quad SPI 4 and 8 bit interface QSPI Flash Boot Mode
SD v2.0 and 3.0 4-bit interface SD Flash Boot Mode
eMMC v4.51 8-bit interface eMMC v4.51 Boot Mode
System Monitoring
PMC SYSMON Voltage and temperature monitor Versal Adaptive SoC System Monitor Architecture Manual (AM006)
PMC ClkMon Clock monitor Clock Monitor
Security Resources
Device security Security management Security Management
AES-GCM Security engine for encryption and decryption PMC AES-GCM
SHA3-384 Secure hash algorithms PMC SHA3-384
RSA/ECDSA Security public-key cryptography engine with authentication algorithms PMC RSA/ECDSA
TRNG True random number generator PMC True Random Number Generator
PUF Physical unclonable function PMC Physically Unclonable Function
BBRAM Battery-backed RAM and controller Battery-Backed RAM
eFUSE Cache and controller  
Timers, Counters, and RTC
RTC Battery backup counter for time keeping Real-Time Clock
I/O Peripheral Controllers
PMC GPIO General purpose I/O controller (52 channels) GPIO Controller
PMC I2C I2C controller I2C Controller
Resets and Clocks
Resets PMC reset controller Resets
Clocks PMC clock controller Clocks
Test and Debug
CoreSightâ„¢ Software debug CoreSight Architecture
Debug packet controller (DPC) Debug packet controller; connected to the PMC main switch, JTAG, Aurora HSDP, and PL Debug Packet Controller
Aurora HSDP interface Serial high-speed debug port Debug Packet Controller
JTAG TAP controller Serial test and debug JTAG TAP Controller
Arm DAP controller Debug access port controller Arm DAP Controller