The system-level registers related to the QSPI controller are listed in the following table.
| Register Name | Description | Access Type |
|---|---|---|
| Clocks and reset control registers in the CRP register module | ||
| QSPI_REF_CTRL | QSPI reference clock frequency control | RW |
| RST_QSPI | QSPI reset control bit | RW |
| DMA transaction control registers in PMC_IOP_SLCR | ||
| QSPI_Coherent | Define transaction coherency and buffer-ability policy | RW |
| QSPI_Route | Route through FPD CCI (APU L2- cache coherent) or bypass it (non-coherent) | RW |
| QSPI_QoS | QoS traffic type; recommend setting to best effort, BE | RW |
| PMC MIO Pin Routing control registers in PMC_IOP_SLCR | ||
|
PMC_IOP_SLCR |
Control the MIO pin routing | RW |