For clock frequencies greater than 25 MHz, the DLL generates the clock for the TX interface that drives the command and data output signals.
- DLL_IO_CLK to the SCLK clock output pad
- DLL_TX_CLK to the TX interface for clocking-out the command and data output pads
The DLL_TX_CLK does not affect the SCLK output.
The timing of the DLL_TX_CLK relative to the DLL_IO_CLK is adjusted using a 180-tap unit. The TX tap for DLL_TX_CLK is selected by the SD_eMMC [sel] bit field. The clock frequency determines the number of useful taps.
- 200 MHz: 8 taps
- 100 MHz: 15 taps
- 50 MHz: 30 taps
- 33 MHz: 45 taps
Example programming values are shown in DLL Programming Example.