The NoC peripheral interconnect (NPI) unit provides software with an AXI programming interface path to configure hardware in the PL and adaptive SoC power domains. The NPI register modules are addressable in a 32 MB memory block. The NPI host controller can receive burst read and write accesses to read and program the NPI registers.
The NPI registers are used for register modules for the memory controllers, miscellaneous integrated hardware, NoC interface units, gigabit transceivers, and I/O clocking units. Access to the NPI host controller is managed by the PMC_NPI_XPPU protection unit. During boot, the NPI is configured when the PMC PLM sends the programmable device image (PDI) NPI partition information to the NPI host controller.
The NPI bus structure is in the adaptive SoC power domain (SPD) and operates completely independent of the NoC interconnect.
Features
The NPI features include:
- Read/write pathway to the programming control and status registers (PCSRs).
- Burst read/write transactions.
- Ordered reads and writes.
- Early write-response with interrupt error signaling is supported by the PLM firmware in the PPU. The PLM performs writes using EWR at times when there are no other transactions occurring.
System Interrupts
If an NPI register module detects an access decode error, or generates a system interrupt, it is signaled back to the NPI host controller. The system interrupts are routed to several destinations as listed in the System Interrupt Controllers section.