The following table lists the system errors routed to the PSM system error accumulator module (EAM).
| Error Name | Software Error Number | PSM Global Register | Description |
|---|---|---|---|
| PS_SW_CR | 0x040 | PSM_ERR1_STATUS[0] | PS software write can set this bit. |
| PS_SW_NCR | 0x041 | PSM_ERR1_STATUS[1] | PS software write can set this bit. |
| PSM_B_CR | 0x042 | PSM_ERR1_STATUS[2] | PSM firmware write can set this bit. |
| PSM_B_NCR | 0x043 | PSM_ERR1_STATUS[3] | PSM firmware write can set this bit. |
| MB_FATAL | 0x044 | PSM_ERR1_STATUS[4] | PSM TMR processor fatal errors. |
| PSM_CR | 0x045 | PSM_ERR1_STATUS[5] | PSM processor correctable error. |
| PSM_NCR | 0x046 | PSM_ERR1_STATUS[6] | PSM processor non-correctable error. |
| OCM_ECC | 0x047 | PSM_ERR1_STATUS[7] | OCM ECC non-correctable error |
| L2_ECC | 0x048 | PSM_ERR1_STATUS[8] | APU L2-cache ECC non-correctable error. |
| RPU_ECC | 0x049 | PSM_ERR1_STATUS[9] | ECC errors during an RPU memory access. Floating-point operation exceptions. RPU APB register access error. |
| RPU_LS | 0x04A | PSM_ERR1_STATUS[10] | RPU lockstep errors from RPU. The lockstep error is not initialized until the RPU clock is enabled. Consequently, error outcomes are masked by default and are expected to be unmasked after processor clock is enabled and before its reset is released. |
| RPU_CCF | 0x04B | PSM_ERR1_STATUS[11] | RPU common cause failures (CCF) ORed together. The CCF error register with the masking capability resides in the RPU. |
| GIC_AXI | 0x04C | PSM_ERR1_STATUS[12] | APU GIC AXI error by the AXI access port such as SLVERR or DECERR. |
| GIC_ECC | 0x04D | PSM_ERR1_STATUS[13] | APU GIC ECC non-correctable RAM error. |
| APLL_LOCK | 0x04E | PSM_ERR1_STATUS[14] | APU PLL (APLL) lock error is asserted while locking or when APLL looses lock. |
| RPLL_LOCK | 0x04F | PSM_ERR1_STATUS[15] | RPU PLL (RPLL) lock error is asserted while locking or when looses lock. |
| CPM_CR | 0x050 | PSM_ERR1_STATUS[16] | CPM correctable error. |
| CPM_NCR | 0x051 | PSM_ERR1_STATUS[17] | CPM non-correctable error. |
| LPD_APB | 0x052 | PSM_ERR1_STATUS[18] |
OR of errors detected by these LPD APB programming interfaces: |
| FPD_APB | 0x053 | PSM_ERR1_STATUS[19] |
OR of errors detected by these FPD APB programming interfaces: |
| LPD_PAR | 0x054 | PSM_ERR1_STATUS[20] | LPD AXI main interconnect parity error. |
| FPD_PAR | 0x055 | PSM_ERR1_STATUS[21] | FPD AXI main interconnect parity error. |
| IOP_PAR | 0x056 | PSM_ERR1_STATUS[22] | LPD IOP interconnect parity error. |
| PSM_PAR | 0x057 | PSM_ERR1_STATUS[23] | PSM interconnect parity error. |
| LPD_TO | 0x058 | PSM_ERR1_STATUS[24] | LPD interconnect ePort mission errors including timeout, address decode error, etc. |
| FPD_TO | 0x059 | PSM_ERR1_STATUS[25] | FPD interconnect ePort mission errors including timeout, address decode error, etc. |
| PSM_TO | 0x05A | PSM_ERR1_STATUS[26] | PSM interconnect ePort mission errors including timeout, address decode error, etc for PSM local, global, MDM, PSM interfaces. |
| XRAM_CR | 0x05B | PSM_ERR1_STATUS[27] | Accelerator RAM (XRAM) correctable error. |
| XRAM_NCR | 0x05C | PSM_ERR1_STATUS[28] | Accelerator RAM (XRAM) non-correctable error. |
| reserved |
0x05D |
PSM_ERR1_STATUS[31:29] | reserved. |
| LPD_SWDT | 0x060 | PSM_ERR2_STATUS[0] | LPD system watchdog timer error. |
| FPD_SWDT | 0x061 | PSM_ERR2_STATUS[1] | FPD system watchdog timer error. |
| reserved | 0x062 to 0x071 | PSM_ERR2_STATUS[17:2] | reserved. |
| LPD_XMPU | 0x072 | PSM_ERR2_STATUS[18] | LPD XMPU read, write, security violation errors and register access error. |
| LPD_XPPU | 0x073 | PSM_ERR2_STATUS[19] | LPD XPPU violations and errors. |
| FPD_XMPU | 0x074 | PSM_ERR2_STATUS[20] | FPD XMPU violations and errors. |
| reserved | 0x075 to 0x07F | PSM_ERR2_STATUS[31:21] | reserved. |