SoC Hardware Overview

Versal Adaptive SoC Technical Reference Manual (AM011)

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The SoCs include extensive functionality for high-end applications that need scalable processing power, integrated functional units, and scalable programmable logic that can be dynamically configured and reconfigured during normal system operation.

The SoC architecture includes a rich set of integrated hardware components and many user-programmable design options for many system-level solutions. Each device incorporates a processing system, programmable logic, a platform management controller, and various integrated hardware subsystems and peripherals. The processing system and programmable logic can be selectively initialized and configured to accommodate different functional and power requirements required by the system solution.

All SoCs include a processing system, a platform management controller, a NoC interconnect, one or more DRAM memory controllers, and various I/O buffers. Device options can include hardware accelerators, communication interfaces, and more. The functionality of the platform management controller (PMC) and processing system is included in the TRM with documentation links for other subsystems. The device options are mentioned in the TRM. They are listed on a per device basis in the Versal Architecture and Product Data Sheet: Overview (DS950).

Processing System

The processing system (PS) provides general-purpose, high-performance compute power with familiar operating environments. The processing system includes the multicore application processing unit (APU) and multicore real-time processing unit (RPU). Linux and bare-metal software stacks can execute in the APU and RPU in a homogeneous or a heterogeneous environment.

The APU is tightly coupled to a coherent interconnect with system cache to provide high-performance software compute power. The APU is located in the full power domain (FPD).

The RPU includes tightly-coupled memories (TCMs) and is placed close to the on-chip memory (OCM) for deterministic software execution rates in a standard programming environment. The RPU and OCM are located in the low-power domain (LPD).

For system software topics, see the Versal Adaptive SoC System Software Developers Guide (UG1304).

Application Processing Unit

The APU is based on two or four Arm® Cortex®-A72 CPU cores that include the Arm A64 instruction set in the v8-A architecture. The APU is tightly coupled to the cache coherent interconnect (CCI) that is surrounded by a system memory management unit (SMMU) for other transaction hosts including DMA units and other system processors. The CCI includes the L2 system cache memory with ECC to form a tightly-coupled coherent system. The APU includes the Arm generic interrupt controller (GIC-500) to manage shared and system interrupts.

The APU can be used for computations, control-plane applications, operating systems, communications interfaces, and more. The TRM describes the system architecture around the APU.

Real-time Processing Unit

The RPU processor is based on two Arm Cortex-R5F CPU cores that can operate in dual or lockstep mode. Each CPU includes separate L1 instruction and data caches and TCMs that are dedicated to their RPU cores to narrow down the deterministic behavior for real-time data processing applications. The CPUs feature out-of-order execution that is coupled with a single/double precision floating point unit (FPU). The processor also includes a general interrupt controller (GIC PL-390) to manage shared and system interrupts. System memory space is cacheable, but the TCM memory space is non-cacheable.

The RPU provides predicable software execution times for real-time applications. Linux and bare-metal software stacks execute in the APU and RPU in a homogeneous or a heterogeneous environment. See the Versal Adaptive SoC System Software Developers Guide (UG1304) for software topics.

NoC Interconnect

The NoC interconnect is pervasive across the device to connect the APU, RPU, and other processors to the DDR memory controllers and other functionality in and around the programmable logic. The interconnect is included in the Interconnect section with details described in the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).

Programmable Logic

The PL is a scalable structure that provides the ability to create many possible functions. The integrated hardware options have interconnect interfaces and connections to the PL. The PL I/O includes both LVCMOS buffers and gigabit transceivers that cover a wide range of applications and frequencies. For more information, see Programmable Logic Overview.

DDR Memory Controller

The device includes one or more DDR4/LPDDR4 memory controllers that is accessible via the NoC.

High-bandwidth Memory Interface

Some devices include one or more high-bandwidth memory (HBM) interfaces that attach to the NoC interconnect and drive I/O buffers to the HBM die within the device. See High-Bandwidth Memory Interface.

Platform Management Controller

For hardware boot, the PMC includes a deeply embedded ROM code unit (RCU) processor. The PMC also includes a platform processing unit (PPU) that executes the platform loader and manager (PLM) firmware that is responsible for software boot, device configuration, partial-reconfiguration, and other platform management tasks.

The PLM also downloads firmware into the processing system management (PSM) controller from the boot device. The PMC is further described in the Platform Management Controller chapter.

Programmable Logic

The programmable logic supports AXI SmartConnect core functionality that can be instantiated using a library of AMD LogiCORE™ IPs. The AXI SmartConnect core can be independent within the PL or extended and attached to the processing system through several AXI interfaces with and without coherency with the APU system cache.

All devices are based on the NoC interconnect to link processors and DMA units to system memory, other processors, and other resources within the device and to external devices with the various implementations of a coherent module with PCIe® (CPM), a device option.

Each device has one or more DDR memory controllers attached to the NoC interconnect. The HBM interface is a device option with one or more HBM controllers.

The size and composition of the PL, the number of memory controllers, the amount of I/O, and the integrated hardware blocks varies by device and are defined in the Versal Architecture and Product Data Sheet: Overview (DS950).

Device Boot

The hardware boot processor, device configuration, and device monitoring units are managed by several processors.

The BootROM code is the first to run after a device-level reset. The RCU BootROM code initializes the device, enables the boot interface, and accesses the boot device header from the flash device. After the hardware boot, the RCU has loaded the platform loader and management firmware into the PMC processor.

System Monitoring

The system is monitored during runtime to detect errors and provide the necessary means to address the errors as a part of the security, reliability, and safety requirements. The configuration, bring-up, and general platform management tasks include reset, clocking, power management, and system monitoring. The PLM and PSM firmware monitors the system during its runtime to detect errors and provide the necessary means to address the errors as a part of the security, reliability, and safety requirements.

Integrated Hardware Options

Coherent Module with PCIe

The coherent module with PCIe (CPM) interconnect is a device option that provides coherency between the PCIe controllers, a PL processor, and the PS. The CCIX interconnect adds memory coherency with external devices over PCIe. There are multiple types of CPM modules:

  • CPM4 with PCIe 4.0 and CCIX 1.0 interconnect (device option in Versal adaptive SoC)
  • CPM5 with PCIe 5.0 and CCIX 1.1 interconnect (device option in Versal adaptive SoC)

See Integrated Hardware Options for more information.