OSPI Flash Interface Signals

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID

AM011

Release Date

2023-10-05

Revision

1.6 English

The following table lists the OSPI flash interface signals. For I/O interface pin planning, see the MIO-at-a-Glance Tables. The OSPI I/O interface is only available on the PMC MIO pins. The interface is not available on the LPD MIO or the PL EMIO. The OSPI flash interface is a boot interface (see OSPI Flash Boot Mode).

Table 1. OSPI Flash Interface Signals
Signal Name	Description	MIO-at-a-Glance Table	I/O
OSPI_CLK	Clock output.	CLK	Output
OSPI_IO[0] OSPI_IO[1] OSPI_IO[2] OSPI_IO[3] OSPI_IO[4] OSPI_IO[5] OSPI_IO[6] OSPI_IO[7]	I/O signals.	IO 0 IO 1 IO 2 IO 3 IO 4 IO 5 IO 6 IO 7	I/O
OSPI_DS	Read data strobe data strobe input, supports the DDR option in octal SPI boot mode. The octal SPI compatible flash must support SDR at power on. During the RCU boot phase initial checks SDR is required, then the PPU can switch the flash to DDR mode for faster boot time.	DS	Input
OSPI_CS0_b	Single device and stacked lower device chip select. Active-Low.	CS0	Output
OSPI_CS1_b	Stacked upper device chip select. Active-Low.	CS1	Output
OSPI_RST_b	Reset output to the OSPI flash device. Active-Low. This reset output signal is generated using the PMC GPIO controller, not the OSPI controller. During OSPI boot process, the RCU asserts and then deasserts the reset output by accessing the PMC GPIO controller.	RST	Output

Note: There is no built-in support for sensing a write protection (WP) signal from the flash device. A GPIO pin can be used to sense the state of a WP input signal.