Test and Debug Implementations

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
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1.6 English

The following table shows the test and debug implementations.

Table 1. Test and Debug Implementations
Device Generation PMC Integrated Debug Debug Packet Controller (DPC) CoreSightâ„¢ DAP Controller CoreSight Embedded Logic Analyzer CoreSight Logic Analyzer Kit CoreSight Stream
UltraScale+ MPSoC PMU architecture and features are different than the PMC. Not available. Included on PS JTAG chain. tbd tbd tbd
Versal device High-speed debug port, HSDP, provides a pathway to the GTY and GTYP transceivers for the Aurora packet-based debug unit (AMD, v1.0). Connected to the PMC main switch, JTAG, Aurora HSDP, and PL. CS_SoC-400, TM100. Arm, r3p2-00rel1

First controller on the JTAG chain.

CoreSight embedded logic analyzer, ELA-500, TM300. (Arm, r2p2-00rel0). CoreSight logic analyzer kit LAK-500 A/I. (Arm, r1p0-00rel0).

CoreSight Stream (STM-500, TM963)
(Arm, r0p1-00rel1).