The following table shows the test and debug implementations.
| Device Generation | PMC Integrated Debug | Debug Packet Controller (DPC) | CoreSight™ DAP Controller | CoreSight Embedded Logic Analyzer | CoreSight Logic Analyzer Kit | CoreSight Stream |
|---|---|---|---|---|---|---|
| UltraScale+ MPSoC | PMU architecture and features are different than the PMC. | Not available. | Included on PS JTAG chain. | tbd | tbd | tbd |
| Versal device | High-speed debug port, HSDP, provides a pathway to the GTY and GTYP transceivers for the Aurora packet-based debug unit (AMD, v1.0). | Connected to the PMC main switch, JTAG, Aurora HSDP, and PL. | CS_SoC-400, TM100. Arm,
r3p2-00rel1 First controller on the JTAG chain. |
CoreSight embedded logic analyzer, ELA-500, TM300. (Arm, r2p2-00rel0). | CoreSight logic analyzer kit LAK-500 A/I. (Arm, r1p0-00rel0). |
CoreSight Stream (STM-500, TM963) |