Message Passing Architecture

Message Passing Architecture - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID

AM011

Release Date

2025-03-11

Revision

1.7 English

The messaging system connects eight agents together in a mesh configuration. The message passing between agents can be done exclusively between the sources and destinations by programming the 128 permission apertures in the LPD_XPPU that correspond to the 0xFF30_0000 to 0xFF30_01FF memory range.

The IPI does not control the content of the message buffers. It is up to the source and destination processor agent software to define the back-and-forth interrupt signaling and the content put into the request and response message buffers. The content of the message buffers does not affect the hardware; it is only written and interpreted by the processors. The use of the message buffers is optional.

The following figure illustrates the IPI message passing architecture for an agent.

Figure 1. IPI Message Passing Diagram

The example in this section shows the message buffer address offsets and access types for the APU assigned as the IPI_2 agent. The other IPI_x agents can be assigned as needed; this includes additional PSM or PMC agents. All buffers are 32 bytes.

Table 1. IPI Message Buffer Example - APU Assigned to IPI 2
Offset Address	Buffer Type	Source Agent		Destination Agent
Offset Address	Buffer Type	Name	Access Type	Name	Access Type
`0x0840` `0x0860`	Request Response	APU Example (assigned to IPI_2)	RW R	PMC	R RW
`0x0800` `0x0820`	Request Response		RW R	PSM	R RW
`0x0880` `0x08A0`	Request Response		RW R	IPI_0	R RW
`0x08C0` `0x08E0`	Request Response		RW R	IPI_1	R RW
`0x0900` `0x0920`	Request Response		RW R	APU this example	R RW
`0x0940` `0x0960`	Request Response		RW R	IPI_3	R RW
`0x0980` `0x09A0`	Request Response		RW R	IPI_4	R RW
`0x09C0` `0x09E0`	Request Response		RW R	IPI_5	R RW