PL Interconnect Interfaces

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

There are several AMBA® interface channels between the PS and PL.

The PL interfaces are summarized here and are shown in several block diagrams, including in the PMC-PS-CPM Interconnect Diagram section.

  • PL to PS Interfaces
    • PL_ACE_FPD provides AXI coherency extension (ACE) to FPD cache coherency interconnect (CCI)
    • PL_ACP_FPD provides an accelerator coherency port (ACP) to the APU MPCore L2 cache snoop control unit
    • PL_ACELITE_FPD provides an I/O cache coherent port to SMMU and CCI
    • PL_AXI_FPD connects to the FPD main switch
    • PL_AXI_LPD connects to the LPD main switch

The LPD and FPD each have an AXI interface channel to the PL. The data width on the PS side is always 128 bits. The PL interface data width can be configured as 32, 64, or 128 bits as defined in the FPD_AXI_PL_Width register.

  • PS to PL Interfaces section
    • FPD_AXI_PL: interface AXI port from FPD main switch to PL
    • OCM_SW_AXI_PL: interface AXI port from LPD OCM switch to PL

Disabled Signal to PL Held High

When a controller or a block in the PMC or PS is disabled or powered-down, its signals to the PL are held High.