PSM Global Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID

AM011

Release Date

2023-10-05

Revision

1.6 English

The PSM global registers help to control and status the following.

Processor controls and status
APU power state
Boot-related errors detected
General storage registers
Power states and control requests
Isolation and reset requests
Power-down control

PSM Global Register Set

The entire PSM global register set is summarized in the following table.

Table 1. PSM Global Register Set
Register Name	Offset Address	Access Type	Description
Miscellaneous
GLOBAL_CTRL	`0x0000`	RW, R	APB destination error enable, FW loaded, PSM R/W QoS, PSM sleep, wake status, and clock control
APU_PWR_STATUS_INIT	`0x0008`	RW	APU 0 and 1 power state value
APB_ISR APB_IMR APB_IER APB_IDR	`0x0010`+	R, W1C R W W	APB programming interface address decode error
PS_SW_ERR	`0x0020`	RW	Software errors detected by PSM
PSM_BOOT_SERV_ERR	`0x0024`	RW	Boot and service errors detected by PSM
32-bit Storage Registers
GLOBAL_GEN_STORAGE0 GLOBAL_GEN_STORAGE1 GLOBAL_GEN_STORAGE2 GLOBAL_GEN_STORAGE3 GLOBAL_GEN_STORAGE4 GLOBAL_GEN_STORAGE5 GLOBAL_GEN_STORAGE6 GLOBAL_GEN_STORAGE7	`0x0030`+	RW	General 32-bit storage registers.
PERS_GLOB_GEN_STORAGE0 PERS_GLOB_GEN_STORAGE1 PERS_GLOB_GEN_STORAGE2 PERS_GLOB_GEN_STORAGE3 PERS_GLOB_GEN_STORAGE4 PERS_GLOB_GEN_STORAGE5 PERS_GLOB_GEN_STORAGE6 PERS_GLOB_GEN_STORAGE7	`0x0050`+	RW	General 32-bit storage registers. The persistent storage registers are only reset by an external POR.
Power State Status
PWR_STATE AUX_PWR_STATE	`0x0100` `0x0104`	R	Power and retention states for power islands and memories
Power, Isolation, Reset, and Wake-up Requests
REQ_PWRUP_ISR REQ_PWRUP_IMR REQ_PWRUP_IER REQ_PWRUP_IDR	`0x0110`+	R, W1C R W W	System software power down requests: - APU 0, APU 1, APU L2 cache - RPU cores, TCM banks - OCM banks, GEM 0, GEM 1, FPD
REQ_PWRDWN_ISR REQ_PWRDWN_IMR REQ_PWRDWN_IER REQ_PWRDWN_IDR	`0x0210`+	R, W1C R W W	System software power up requests
REQ_ISO_ISR REQ_ISO_IMR REQ_ISO_IER REQ_ISO_IDR	`0x0310`+	R, W1C R W W	FPD isolation request
REQ_SWRST_ISR REQ_SWRST_IMR REQ_SWRST_IER REQ_SWRST_IDR	`0x0410`+	R, W1C R W W	Subsystems and Power Islands: - APU 0, APU 1, APU MP, RPU - GEM 0, Gem 1, USB 2.0 - I/O peripherals, PS, LPD, FPD
REQ_WAKEUP_ISR REQ_WAKEUP_IMR REQ_WAKEUP_IER REQ_WAKEUP_IDR	`0x0700`+	R, W1C R W W	Wake-up requests: - APU 0, APU 1 from APU GIC - RPU 0, RPU 1 from RPU GIC - USB 2.0 CoreSight wake-up requests: - GPR for APU 0, APU 1 Debug power for: - APU 0, APU 1, RPU, FPD
REQ_CTRL_ISR REQ_CTRL_IMR REQ_CTRL_IER REQ_CTRL_IDR	`0x0714`+	R, W1C R W W	Power-down requests: - From APU 0, APU 1 - From RPU 0, RPU 1 Reset request from RPU 0 Warm reset request: - For APU 0, APU 1 from APU MP - For APU 0, APU 1 from APU debug FPD power alarm
Miscellaneous
DBG_PWR_ACK	`0x0808`	RW	Debug power-up acknowledge: - APU 0, APU 1 - RPU - FPD
SAFETY_CHK	`0x0A00`	RW	Safety check register