Debug Topics

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The debug capabilities span from basic hardware to advanced processing systems.

There are various boot and configuration modes and the boot sequence that must successfully be executed for the device to become operational.

JTAG Interface

The JTAG interface pins are part of the PMC dedicated pins. The JTAG interface provides access to several debug resources:
  • Boundary-scan
  • System-level functions
  • Access to Arm DAP controller for processor debug

CoreSight Debug Environment

The CoreSight debug environment includes intrusive and non-intrusive interfaces into the processors in the processing system and programmable logic (PL); the CoreSight debug features provide heterogeneous software debug between the RPU, APU, and PL.

The CoreSightâ„¢ debug environment attaches to the processor debug hooks in the RPU and APU plus an interface to the PL for additional processors in a chip-wide heterogeneous system.

There are also hardware capture points in the network on chip (NoC) and AXI interconnects. User-selected capture points in the PL can be defined.

The CoreSight debug environment is controlled via the JTAG DAP controller with data transfers via the debug packet controller to the Aurora HSDP interface and the DAP controller.