Signals to the Timer

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

Reference Clock Input

The watchdog timer reference clock source is selected between a few sources:

  • APB clock,
  • MIO input signal, or
  • PL EMIO input signal

The register control is in the associated IOP_SLCR or main SLCR register module.

Reset Signals to the Timer

The SWDT timer can be reset by an individual or system reset. The individual reset is controlled by the reset registers in the SWDT register module. The system resets are controlled by the clock/reset register module of the associated power domain (e.g., CRL.RST_LPD_SWDT). Resets are described in the Resets chapter.

Generic Mode Warm Reset to the Timer

For the generic mode, the controller includes a warm reset control in the G_Warm_Reset register.