Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

Resets can be described as three groups.

  • Device-level resets controlled by hardware and software
  • Subsystem resets controlled by software
  • Individual block resets controlled by software

The device-level resets include major subsystems that include the LPD and FPD, the NoC interconnect, and other integrated hardware. The device-level resets are generated by the POR_B input pin, the EAM, and the firmware in the PLM and PSM.

The subsystems are affected by the device-level resets and the individual block resets are affected by device and subsystem resets.

Reset Register Modules

The individual reset controls are managed by the PLM and PSM firmware. The firmware writes to the clock and reset register modules.

  • CRP : device-level and individual PMC block reset control registers
  • CRL : subsystem and individual LPD block reset control registers
  • CRF : individual FPD block reset control registers
  • CPMx_CRX: individual CPM block reset control registers

Device-level Resets

There are two device-level resets.

  • POR: reset and clear almost everything
  • SRST: reset and clear most functionality

The POR and SRST distinction applies to device level resets and the persistent registers.

The device-level resets are generated by hardware reset circuitry, the POR_B device pin, the reset signals from a error accumulator module (EAM), the JTAG controller, and the software written PMC registers.

  • External POR
  • Internal POR

The external POR is controlled by the POR_B device input pin. When the POR_B pin transitions from Low to High, the device starts from the External POR reset state.

The hardware monitors the voltage state of the three PMC power supplies. These must be within their operating range before releasing POR_B. During operation, if one of the power supplies falls below a voltage threshold, then an External POR is generated within the device.

The internal POR can be generated by the PMC error accumulator module (EAM) and by writes to the CRP register module.

The device-level resets are recorded in the reset reason register.

Subsystem Resets

The major reset controls allow software to reset large parts of the LPD and FPD.

These are explained in Subsystem Resets section.

Debug Resets

The CoreSightâ„¢ debugger has access to many resets throughout the device.

The resets are summarized in the Debug Resets section.

Programmers Reset Service Requests

The system software can request that subsystems and some individual blocks be reset. This is done by writing to the PMC and PSM global register sets.

This is explained in Reset Service Requests section.