SPI Controller I/O Signals

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The SPI controller I/O interface is routed to both the PMC MIO pins, LPD MIO pins, and the EMIO signals.

The MIO signals are shown in the MIO-at-a-Glance Tables and all signals are detailed in the following table. The I/O signals are shown in the Functional Diagram.

Table 1. SPI Controller I/O Signals
MIO
Signal Name I/O MIO-at-a-Glance Table Entry
Common Signals

SPI0_SCLK
SPI1_SCLK

I/O SCLK

SPI0_MISO
SPI1_MISO

I/O MISO

SPI0_MOSI
SPI1_MOSI

I/O MOSI

SPI0_CS0_b
SPI1_CS0_b

I/O CS0
Manager-only Signals

SPI0_CS1_b
SPI1_CS1_b

O CS1

SPI0_CS2_b
SPI1_CS2_b

O CS2