System-level Clock and Reset Registers

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The clock and reset control registers are summarized in the following table.

Table 1. I2C Controller System-level Clock and Reset Registers
Register Name Access Type Description Signal Name
PMC_I2C
I2C_REF_CTRL RW Reference clock PMC_I2C_REF_CLK
RST_I2C RW Controller reset PMC_I2C_RESET
LPD_I2C0
I2C0_REF_CTRL RW Reference clock LPD_I2C0_REF_CLK
RST_LPD_I2C0 RW Controller reset LPD_I2C0_RESET
LPD_I2C1
I2C1_REF_CTRL RW Reference clock LPD_I2C1_REF_CLK
RST_LPD_I2C1 RW Controller reset LPD_I2C1_RESET