AMD Adaptive Computing documentation is organized around a set of standard design processes to help you find relevant content for your current development task. You can access the AMD Versal™ adaptive SoC design processes on the Design Hubs page. You can also use the Design Flow Assistant to better understand the design flows and find content that is specific to your intended design needs.
- System and Solution Planning
-
Identifying the components, performance, I/O, and
data transfer requirements at a system level.
Includes application mapping for the solution to PS,
PL, and AI Engine.
The technical reference manual (TRM) describes the overall hardware architecture of the Versal adaptive SoC and provides details on the blocks in the platform management controller (PMC) and in the processing system (PS). The PS includes the real-time processing unit (RPU), application processing unit (APU), and their peripherals.
- Device-level block diagram: SoC Hardware Overview chapter
- High-level Interconnect Diagrams chapter
- Processing System Architecture chapter
- Programmable Logic Overview chapter
- Device I/O Connectivity chapter with I/O buffers and transceivers
- Clocks, Resets, and Power chapter with architectures and controls
There are several device families with different device options. The availability of a specific device option is listed in the Versal Architecture and Product Data Sheet: Overview (DS950). The TRM usually identifies these with the designation: device option.
- Embedded Software Development
-
Creating the software platform from the hardware
platform and developing the application code using
the embedded CPU. Also covers XRT and Graph
APIs.
Embedded software runs in the RPU and APU scalar engines located in the PS.
- Real-time Processing Unit: dual-core Cortex-R5F processor with lock-step option
- Application Processing Unit: dual-core processor
The PMC and PS functional units require device drivers as part of the embedded software stack. Several TRM reference sections focus on content for device driver development. The peripherals in the PMC, LPD, and FPD are described in the following sections:
- Embedded Processor, Configuration, and Security Units
- I/O Peripheral Controllers
- Flash Memory Controllers
The boot hardware modes and functionality are described in the Platform Boot, Control, and Status section of the TRM. Additional TRM sections and chapters describe the interconnect, timers, counters, clocks, resets, and power.
The system software boot up and operating system environments are described in the Versal Adaptive SoC System Software Developers Guide (UG1304). The PMC modules are described in the Embedded Processor, Configuration, and Security Units section.
- Board System Design
-
Designing a PCB through schematics and board
layout. Also involves power, thermal, and signal
integrity considerations.
The TRM includes some important information to help with board design planning and development.
- Boot device interfaces: Boot Modes and Interfaces
- Pin planning for I/O peripherals: Multiplexed I/O Signals and Pins
- Power controls: Power Diagram
- JTAG interface: TAP Controller Instruction Availability
For package and pin information, see the Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013).
The electrical specifications are provided in the applicable Versal device data sheet listed in References.