The global registers serve several purposes.
- Triple module redundant MicroBlaze™ processor controls, QoS for PPU on AXI
- Storage registers (regular and persistent) and error storage for PLM firmware
- Multiboot control
- Mutex registers for processor software
- Isolation and power supply storage
- Power, isolation, reset, wake-up, and PL interrupt registers
- DONE signal control, reset controls
- Error management, firmware error storage registers
- System error registers for PMC EAM
- System interrupt registers
- Soft error mitigation (SEM) in the PL configuration RAM (CRAM)
The platform service request registers allow system software to make power-up, power-down, isolation, and software reset requests by setting bits in the trigger registers.
The PMC global register set is accessed via a 32-bit APB programming interface that can be accessed by any permitted processor.
PMC Global Register Set
The following figure summarizes the entire PMC global register set.
Register Name | Access Type | Description |
---|---|---|
Miscellaneous | ||
GLOBAL_CTRL | RW, R | APB error, PLM firmware is loaded flag, MB status, and MB clock control (GLOBAL_CTRL). |
PMC_MULTI_BOOT | RW | MultiBoot offset address is PMC_MULTI_BOOT[20:0]. For SD/eMMC1 boot modes, the partition type is PMC_MULTI_BOOT[31:28]. |
PPU_TMR_CTRL | RW | LMB ECC error propagation select. |
W1C | APB address decode error, secure stream configuration error, and PUF access error. | |
32-bit Storage Registers | ||
|
RW | Storage registers 0, 1, 2, 3, and 4 are reserved for use by the PLM firmware. There are also PSM_GLOBAL storage registers, see PSM Global Registers. |
|
RW |
Persistent storage registers 0, 1, and 2 are reserved for use by PLM firmware. Persistent storage registers 3 and 4 are available for general use. |
PMC Software Service Errors | ||
PMC_GSW_ERR | RW | General software service errors from PLM. |
Power, Isolation, Reset, and Wake-up Requests | ||
DOMAIN_ISO_STATUS | R | Isolation wall status. |
R | Power supply status. | |
|
R, W1C |
System software power-up requests: |
|
R, W1C |
Power-down requests. |
|
R, W1C |
Isolation requests. |
|
R, W1C |
System software reset requests: |
|
R, W1C |
CoreSight™ wake-up GPR for LPD and CPM. |
Miscellaneous | ||
DDR_RETENTION_CTRL | RW | Hold the XPIO output latched values to support DRAM self-refresh mode so the DDRMC power (SPD) can be shut down. |
DBG_PWR_ACK | RW | CoreSight power-up acknowledge for LPD and CPM. |
SSS_CFG | RW | Secure stream switch interface configuration. |
|
R | PPU TMR redundancy logic status. |
PPU_RST | RW | PPU reset control. |
PPU_RST_MODE | RW | PPU reset mode configuration. |
PPU_AXI_QOS | RW | PPU AXI QoS value. |
SAFETY_CHK | RW | Safety check register. |
PL_STATUS | R | PL reset status. |
DONE | RW | DONE output pin control. |
PL-PS Signals | ||
PMC_PL_GPO | R | See PL-PMC GPI and GPO Port Signals. |
|
R, W1C |
|
Software Mutex Registers | ||
32 Mutex registers: |
RW | Software mutex registers. |
Register Write Locks | ||
PPU_RST_LOCK | RW | Control locking of PPU_RST resettable registers. |
POR_LOCK | RW | Control locking of POR resettable registers. |